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Texas Instruments /MSP432P401Y /FLCTL_A /FLCTL_IE

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Interpret as FLCTL_IE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RDBRST)RDBRST 0 (AVPRE)AVPRE 0 (AVPST)AVPST 0 (PRG)PRG 0 (PRGB)PRGB 0 (ERASE)ERASE 0 (BMRK)BMRK 0 (PRG_ERR)PRG_ERR

Description

Interrupt Enable Register

Fields

RDBRST

If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG
AVPRE

If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG
AVPST

If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG
PRG

If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG
PRGB

If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG
ERASE

If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG
BMRK

If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG
PRG_ERR

If set to 1, enables the Controller to generate an interrupt based on the corresponding bit in the FLCTL_IFG

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data